1. Field of the Invention
The present invention generally relates to memory device that has user programmable alternating current (AC) timings and, more particularly, to a programmable SRAM memory which uses either default timing specifications stored in a fuse bank or allows the user to customize the timing specifications of individual pins via a JTAG instruction.
2. Description of the Related Art
Static random access memory (SRAM) is a type of high speed memory wherein each bit is represented by the state of a circuit with two stable states. Such a "bistable" circuit can be built with four transistors (for maximum density) or six (for highest speed and lowest power). SRAM retains data bits in its memory as long as power is being supplied. Unlike dynamic RAM (DRAM), which stores bits in cells made up of a capacitor and a transistor, SRAM does not have to be periodically refreshed. Static RAM provides faster access to data but is more expensive than DRAM. SRAM is commonly used for a computer's level two (L2) cache memory. The function of the L2 cache is to stand between DRAM and a computer's central processing unit (CPU), offering faster access than DRAM. Individual SRAM memory cells are typically configured in arrays and addressable subarrays that may be as large as 16 MB or more.
The timing requirements between various ports or pins accessing the various address lines and data lines is critical if the chip is to function properly. Therefore chips need to be tested to ensure their integrity. In the past chips were tested with a "bed of nails" technique wherein physical probes would come into contact with various points or test pads on the chip surface to input test signals and to measure output signals to test the inner workings of the chip. However, with the emergence of smaller and more densely integrated chips, including SRAM chips, the ability to test the chips in a non-invasive manner is desirable.
One such non-invasive testing technique that has emerged is the so-called Joint Test Action Group (JTAG) interface. JTAG is a state machine interface that is incorporated right into the design of many modern chips. This interface is a standard specified in "IEEE Standard Test Access Port and Boundary-Scan Architecture", IEEE Std 1149.1-1990 (includes IEEE Std 1149.1a-1993), published by the Institute of Electrical and Electronics Engineers, Inc. on Oct. 21, 1993. With the JTAG protocol access to all pins is achieved electronically through boundary scan principles. A JTAG interface requires the addition of several additional dedicated JTAG pins such as TMS (test mode select), TCK (test clock), TDI (test data in), and TDO (test data out).
In brief, the JTAG protocol comprises a set of standard instruction codes which when input causes test data applied to the test data in (TDI) pin to be scanned through various boundary registers by the test clock (TCK) in a programmed manner. Observing the output data at the TDO pin allows one to observe the inner workings of the circuit. The JTAG protocol further reserves a number of codes referred to a "private instructions" which may be defined by the manufacturer.
The JTAG protocol is very versatile. In addition to providing a means for performing diagnostic testing, it is also possible to use the JTAG interface to gain control of various chip functions. For example, U.S. Pat. No. 5,650,734 to Chu et al. discloses a method for using a JTAG state machine to program a programable logic device such as programmable read-only-memories (PROMs). Some types of PROMs may be erased and rewritten by using specified electrical potentials that are higher than normal operating potentials. Wu uses the dedicated JTAG ports on a PROM device to turn on and off erase and program circuitry thus eliminating the need to provide separate pins for these functions. As can be observed from above, JTAG is a versatile protocol having advantages beyond diagnostics.
As previously noted, in modern high speed memories the timings requirements between various pins on the chip is critical if the chip is to function properly. Particularly critical is the set-up and hold time requirements which refers to the time window required for the data inputs to be held stable prior to (set-up) and just after (hold) the control input changes to latch, capture or store the value indicated by the data inputs.
The integrity of data-valid windows poses a significant challenge for high-frequency input/output (I/O) interfaces. This challenge is exacerbated by the fact that the timing of the SRAM chip standing alone may be effected somewhat at the system level (i.e., once the SRAM is integrated as part of an actual cache system the timing requirements may change). Generally, the system-timing requirement for setup and hold is a total data-valid window of approximately 1/3 of the data rate. At a data rate of 200 MHz, the minimum total valid window would be 1.667 ns, or 833 ps of setup time and 833 ps of hold time. Typically, this window is guaranteed by test according to carefully controlled input swings and input slew rates. If any differences in input swings and slew rates occur in a 200 MHz cache system compared to those in the data sheets, the device is still very likely to function properly because of the relatively large setup-and-hold specifications. However, if the cache is sped up to a 1 GHz data rate, the setup-and-hold specifications become 1.67 ps each. Data rates above 1 GHz lead to even more stringent timing requirements. At these speeds, any differences in input signal characteristics between those specified in the data sheet and those in the cache system are likely cause a violation of data setup-and-hold and lead to malfunction.
FIGS. 1A and 1B illustrate how a system malfunction may occur due to setup-and-hold time violations. In FIG. 1A, Data sheet Timings for a SRAM are shown. The signals at the SRAM DQ pad are shown on the left and the corresponding clock and input signals at the DQ register are shown on the right. The shaded region illustrates the margin that the edge-triggered register requires to properly function across process and application variations. Typically, devices are designed with equal setup-and-hold margins. The cache-system timings shown in FIG. 1B illustrates the impact that changing input signal level and slew rate has on I/O circuit operation. The illustrated input characteristics are significantly different from those of the data sheet, yet are entirely possible in the physical environment of any given cache system. This specific set of inputs moves the hold margin within the critical minimum design window shown in the shaded region, causing a system failure to occur.
Hence, as is clear from the foregoing discussion, there is a need in the art to provide a way for an end user of a SRAM module to be able to program or "tweak" the timings of various data or address pins in order to optimize the SRAM module once installed in the final system.